This invention relates to semiconductor memory devices, and more particularly to an N-channel silicon gate MOS read only memory and a process for making it.
Semiconductor memory devices are widely used in the manufacture of digital equipment such as minicomputers and microprocessor systems. Storage of fixed programs is usually provided in these systems by MOS read only memory devices or "ROMs". The economics of manufacture of ROMs, and of mounting them on circuit boards in the system, are such that the number of memory bits per semiconductor chip is advantageously as high as possible. ROMs of up to 32 K bits (32768) are typical at present. Within a few years, standard sizes will progress through 64 K, 128 K, 256 K and 1 megabit. This dictates that cell size for the storage cells of the ROM be quite small. Metal gate ROMs of small size can be relatively easily fabricated in the manner set forth in U.S. Pat. No. 3,541,543, assigned to Texas Instruments; these are usually programmed by the gate level mask. Most microprocessor and computer parts are now made by the N-channel silicon gate process because of the shorter access times provided. In the past, the N-channel process has not been favorable to layout of ROM cells of small size. N-channel ROMs are disclosed in prior applications Ser. No. 762,612, filed Jan. 29, 1977 and Ser. No. 701,932, filed July 1, 1976, assigned to Texas Instruments. A method of programming a ROM by ion implant prior to forming the polysilicon gate is shown in U.S. Pat. No. 4,059,826 to Gerald D. Rogers, assigned to Texas Instruments. Also, previous cells have been programmed at the metal level mask by contact areas between metal lines and polysilicon gates, or by contacts between metal lines and N+ source or drain regions, using excessive space on the chip.
Methods of programming N-channel ROMs by implant through polysilicon gates are shown in prior applications of C-K Kuo, Ser. No. 890,555, Ser. No. 890,556, Ser. No. 890,557, filed Mar. 20, 1978, Ser. No. 900,549, filed Apr. 27, 1978, and of Kuo and Tsaur, Ser. No. 907,236, filed May 18, 1978, all assigned to Texas Instruments. These methods required that no metal overlie the gates and thus "SATO" type processing was used so that no metal was in the ROM array.
It is the principal object of this invention to provide a semiconductor permanent store memory cell of small size which uses a process compatible with the standard high volume N-channel silicon gate process. Another object is to provide a small-area MOS ROM cell which is made by a process compatible with the standard N-channel self-aligned silicon gate manufacturing process and yet allows N+ conductor strips to pass under polysilicon strips without forming gates or contacts.